An experimental approach of Power Proficient, High Gain R-2R Ladder DAC and Designed in 90nm CMOS Technology

1Hara prasad Tripathy, Priyabrata Pattanaik, Susanta Kumar Kamilla

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Abstract:

In present era of communication system there is a long-felt need for broad band transmission of data (i.e. image, audio or video) at a high rate of data transmission. In this paper an 8 bit D/A converter (DAC) is constructed, simulated in Matlab and compared with the other available DACs. The constructed DAC has very low power consumption of around 2.12 mWatt along with the DNL of 0.40 and INL of 0.78.

Keywords:

DAC, DNL, SNR, SFDR, R-2R ladder, Op-Amp, CMOS, INL, DNL.

Paper Details
Month12
Year2019
Volume23
IssueIssue 5
Pages108-117