IMPLEMENTATION OF ARTHEMETIC LOGIC UNIT USING QUATERNARY SIGNED DIGIT NUMBER SYSTEM

Authors

  • M. Anitha Sumathi Reddy Institute Of Technology For Women ,Warangal, Telangana, India Author
  • G.Jhansi rani Sumathi Reddy Institute Of Technology For Women ,Warangal, Telangana, India Author
  • D.Raghava kumara Sumathi Reddy Institute Of Technology For Women ,Warangal, Telangana, India Author
  • Dr. P. Anuradha Sumathi Reddy Institute Of Technology For Women ,Warangal, Telangana, India Author

DOI:

https://doi.org/10.61841/1bh6fe19

Keywords:

quaternary sign digit(QSD), expeditious computation, multiplier, quaternary logic,ALU

Abstract

A new number system for Arithmetic Logic Unit.A major problem in arithmetical operation is binary number system to overcome this problem using signed digit operation for carry free arithmetical in this operation Using QSD system to perform carry free addition ,subtraction and mulitiplication.the QSD number system require different modulo based logic elements for arthemetic logic operation .A carry free addition .subtraction and multiplication operations are achieved using a higher radix numbering system. QSD each bit represent by -3 to +3

.Quaternary Signed Digit (QSD) have a major contribution in higher radix (=4) carry free arithmetical operation addition/,subtraction and multiplication and other Carry free operations. More binary numbers like large number of digits such as 64, 128, or more can be implemented with maintain constant delay and less complexity. So we can design an adder without ripple carry. the quaternary numbers are represented using 3-bit 2’s compliment form of signed digit..

 

Downloads

Download data is not yet available.

References

[1] M. Thoidis, D. Soudris, J. M. Fernandez, A. Thanailakis,“The circuit design of multiple-valuedlogic voltage-mode adders,” 2001 IEEE

[2] A.A.S. Awwal and J.U. Ahmed,“fast carry free adder design using QSD number system” proceedings of the IEEE 1993 national aerospace and electronic conference, vol 2,pp 1085-1090,1993.

[3] Behrooz perhami “generalized signed digit number systems, a unifying frame work for redundant number reperesentation “.IEEE transactions on computers,vol 39,no.1,pp.89-98,January 19990.

[4] O. Ishizuka, A. Ohta, K. Tannno, Z. Tang, D. Handoko, “VLSI design of a quaternary multiplier with direct generation of partial products,”Proceedings of the 27th International Symposium on Multiple-Valued Logic, pp. 169-174, 1997.

[5] A.A.S Awwal, Syed M. Munir, A.T.M. Shafiqul Khalid, Howard E.Michel and O. N. Garcia, “Multivalued Optical Parallel Computation Using An Optical Programmable Logic Array”, Informatica, vol. 24, No.

4, pp. 467-473, 2000.

[6] F. Kharbash and G. M. Chaudhry, “Reliable Binary Signed Digit Number Adder Design”, IEEE Computer Society Annual Symposium on

VLSI, pp 479-484, 2007.

[7] John Moskal, Erdal Oruklu and Jafar Saniie, “Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder”, IEEE International

symposium on Circuits and Systems, pp 1089-1092, 2007.

[8] Kai Hwang, “Computer Arithmetic Principles, Architecture and Design”, ISBN 0-471-03496-7, John Wiley & Sons, 1979.

[9] Nagamani A. N, Nishchai S, “Quaternary High Performance Arithmetic Logic Unit Design”, 14th Euromicro Conference on Digital System Design 2011 IEEE. [2]

[10] Reena Rani, Laxmikant Singh, Neelam Sharma, “FPGA Implementation of fast Adder using Quaternary Sign Digit Number System”, 2009 International comferance on Trend in Eletronic and Photonic Deice & Systems (EECTRO-2009). [3]

[11] Pranali S.Kamble & S.M.Choudhary, “Review of VHDL Implementation of Quaternary Signed Adder System”, International Journal on Advanced Electrical and Electronics Engineering, (IJAEEE), ISSN (Print): 2278-8948, Volume-1, Issue-1, 2012 [4]

[12] Songpol Ongwattanakul Phaisit Chewputtanagul, David J. Jackson, Kenneth G. Ricks, “Quaternary Arithmetic Logic Unit on a Programmable Logic Device”, proc. IEEE conference, 2001.

[13] Jyoti R. Hallikhed, Mahesh R.K., "VLSI Implementation of Fast Addition using Quaternary Signed Digit Number System",International Journal of Ethics in Engineering & Management Education, Vol.2, Issue 5, May 2015.

[14] S. JakeerHussain, K. SreenivasaRao, "Design and implementation of Fast Addition Using QSD for Signed and Unsigned Numbers", International Journal of Engineering Research, Volume No. 3, Issue No: Special2, pp: 52-54, March 2014.

[15] C. V. Sathish Kumar, P. Jaya Rami Reddy, "Implementation of Fast Adder Using QSD for Signed and Unsigned Numbers", International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 11, November 2014.

[16] Kothuru. Ram Kumar, B. Praveen Kumar, "Fast Addition Using QSD VLSI Adder for Better Performance", International Journal of Trend in Research and Development, Volume 2(6), Nov-Dec 2015.

[17] G. Manasa, M. DamodharRao, K. Miranji, "Design and Analysis of Fast Addition Mechanism for Integers using Quaternary Signed Digit Number System", International Journal of VLSI and Embedded Systems-IJVES, Vol 05, Article 09455, October 2014.

Downloads

Published

31.10.2020

How to Cite

M. Anitha, G.Jhansi rani, kumara, D., & P. Anuradha. (2020). IMPLEMENTATION OF ARTHEMETIC LOGIC UNIT USING QUATERNARY SIGNED DIGIT NUMBER SYSTEM. International Journal of Psychosocial Rehabilitation, 24(8), 15363-15375. https://doi.org/10.61841/1bh6fe19