IMPLEMENTATION OF ARTHEMETIC LOGIC UNIT USING QUATERNARY SIGNED DIGIT NUMBER SYSTEM
DOI:
https://doi.org/10.61841/1bh6fe19Keywords:
quaternary sign digit(QSD), expeditious computation, multiplier, quaternary logic,ALUAbstract
A new number system for Arithmetic Logic Unit.A major problem in arithmetical operation is binary number system to overcome this problem using signed digit operation for carry free arithmetical in this operation Using QSD system to perform carry free addition ,subtraction and mulitiplication.the QSD number system require different modulo based logic elements for arthemetic logic operation .A carry free addition .subtraction and multiplication operations are achieved using a higher radix numbering system. QSD each bit represent by -3 to +3
.Quaternary Signed Digit (QSD) have a major contribution in higher radix (=4) carry free arithmetical operation addition/,subtraction and multiplication and other Carry free operations. More binary numbers like large number of digits such as 64, 128, or more can be implemented with maintain constant delay and less complexity. So we can design an adder without ripple carry. the quaternary numbers are represented using 3-bit 2’s compliment form of signed digit..
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