A Case Study on VLSI Floor Planning Problem Using Metaheuristic Algorithms

Floor planning is an essential trouble in very massive scale incorporated-circuit layout automation because it determines the performance, size, yield, and reliability of VLSI chips. From the computational point of view, VLSI floor planning is an NP-hard hassle. Modern very huge scale integration technology is primarily based on constant-define floor plan constraints, normally with an goal of minimizing area and wirelength between the modules. This survey paper gives an up to date account on diverse metaheuristic algorithms used to SOI. As technology advances, circuit sizes and layout complexity in cutting-edge VLSI layout are increasing rapidly. To manage the design complexity, hierarchical design and reuse of IP modules turn out to be popular, which makes floor planning or placement a lot extra crucial than ever [1].