Influence of spacer on symmetrical stepped InGaAs/InP DGMOSFET for enhancement of the device performance.

In this work the impact of spacer in InGaAs/InP hetero stepped double gate MOS transistor is investigated by a 2D TCAD device simulator. To minimize the short channel effects (SCEs), underlap technique is used symmetrically in either side of the gate. However, it considerably decreases the On current due to enhanced channel resistance. Thus the spacers on underlap region are one of the solutions to overwhelm these problems. Therefore, difficulties associated with conventional underlap DG MOSFET can be eliminated with significant improvement in On current and intrinsic gain. Further, to reduce the punch-through effect, stepped gate concept is integrated in the double gate MOSFET to attain a better control on the channel carriers that eventually reduces the leakage current. So this paper presents a comparison made between symmetric spacer underlap hetero stepped double gate (SSUHS-DG) MOSFET and hetero stepped double gate (HS-DG) MOSFET; so far SSUHS-DG MOSFET offers better device performance