Satya Ranjan Das, Priyabrata Pattanaik

Abstract

This work presents the designing of an alternative multiply-accumulate (MAC) unit fused by redundant arithmetic. A “double carry-save output encoding” is used in this design. It is a suitable structure for reconfigurable systems which is based on 6 input LUT. A high performance system could be obtained without any pipelining by the employment of (6,3) counters in the reduction of accumulation operations and partial products as a logic depth which is provided is least in amount. The carry propagation does not affects this proposed system as MAC structure implements a redundant arithmetic scheme. The MAC unit designed here comprise of an accumulate output of 40 bits and a multiplier of s16x16 bits. The synthesis is done on ‘AlteraTM Stratix III FPGA board’ and better performance in comparison with conventional pipelines is achieved.

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