Low Power and Low Latency Memristive-Ternary Content Addressable Memory Design Using Absolute Path Search Optimization (APSO) Algorithm

In this work, a Low Latency and low power use of memristive ternary content addressable memory (MTCAM) design is implemented for utilizing new optimization method specifically Absolute Path Search Optimization (APSO) algorithm. The outline of a proposed memory has been altered by the expansion of all validation supervisors required by the equipment usage of switching devices in the memory. In addition, aAPSO has been incorporated into real time application to permit a memory design based on full self-rule. Therefore, compared with the conventional design comprising of a switching-block and an isolated memory, this new method will prompt an imperative decrease of data searching among the memory read and write procedure. The proposed work is depicted utilizing Verilog language, synthesized and actualized utilizing Xilinx ISE suite based Field Programmable Gate Array (FPGA) devices. Synthesis results demonstrate that the proposed configuration accomplishes higher efficiency than the previous executions by decreasing area while keeping up a moderate throughput/Look Up Table (LUT) ratio. The proposed configuration is additionally more productive as far as power utilization.