MPEG-4 Motion Pictures Enciphering and Deciphering Techniques Using VHDL

This paper is a straightforward model of complex real-time MPEG-4 video encoding and deciphering systems based on VHDL, mainly focused on energy efficiency, low power and assets on FPGA. In this add to a MPEG-4 video Encoder/decoder which works at fundamental level of 4:2:0 720 x 480 at 29:97 edges for each second. This configuration is essentially centered on vitality effectiveness. The decoder and encoder for video are the important parts of its codec module. The module of encoder contains transformation of frames, Segmentation, pre-handling, discrete cosine transform and Inverse DCT Compression.